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研究关键路径问题是时延驱动集成电路设计的基础。提出了一种改进的关键路径算法，实现了对任意的有向图提取Ｋ条关键路径。算法速度快，实用性强，对高密度高速度集成电路的时延分析与优化具有重要的应用价值
Researching the critical path problem is the basis of the design of delay-driven integrated circuits. An improved critical path algorithm is proposed, which can extract K critical paths from any directed graph. The algorithm is fast and practical, which has important application value in the analysis and optimization of delay of high density and high speed integrated circuits