论文部分内容阅读
研究了利用Cu/Sn对含硅通孔(TSV)结构的多层芯片堆叠键合技术。采用刻蚀和电镀等工艺,制备出含TSV结构的待键合芯片,采用扫描电子显微镜(SEM)对TSV形貌和填充效果进行了分析。研究了Cu/Sn低温键合机理,对其工艺进行了优化,得到键合温度280℃、键合时间30 s、退火温度260℃和退火时间10 min的最佳工艺条件。最后重点分析了多层堆叠Cu/Sn键合技术,采用能谱仪(EDS)分析确定键合层中Cu和Sn的原子数比例。研究了Cu层和Sn层厚度对堆叠键合过程的影响,获得了10层芯片堆叠键合样品。采用拉力测试仪和四探针法分别测试了键合样品的力学和电学性能,同时进行了高温测试和高温高湿测试,结果表明键合质量满足含TSV结构的三维封装要求。
The multi-layer chip stack bonding technology using Cu / Sn for TSV structures has been investigated. The TSV structure to be bonded was prepared by etching and electroplating process. The morphology and filling effect of TSV were analyzed by scanning electron microscope (SEM). The low temperature bonding mechanism of Cu / Sn was studied and its process was optimized. The optimum conditions for bonding temperature 280 ℃, bonding time 30 s, annealing temperature 260 ℃ and annealing time 10 min were obtained. Finally, the multi-layer stacking Cu / Sn bonding technology was analyzed. The EDS analysis was used to determine the atomic ratio of Cu and Sn in the bonding layer. The effects of Cu layer and Sn layer thickness on the bonding process were studied, and 10-layer stacked chips were obtained. The mechanical and electrical properties of the bonded samples were tested by the tensile tester and the four-probe method. The high-temperature and high-temperature high-humidity tests were performed simultaneously. The results showed that the bonding quality satisfied the 3D packaging requirements of the TSV structure.