A vector inserting TPG for BIST design with low peak power consumption

• 作 者: Tan Enmin Song Shengdong Shi Wenkang
• 机 构: School of Electronics and Electric Engineering, Shanghai Jiaotong University, Shanghai 200030, P.R.C
• 出 处: 高技术通讯（英文版）
• 发表日期: 2007年4期
• 关键词: low peak power consumption design built-in self-test(BIST) test pattern generato

A test pattem generator(TPG)which can highly reduce the peak power consumption during built-in self-test(BisT)application is proposed.The pmposed TPG,called Lppe-TPG,consists of a linear feedback shift register(LFSR)and some control circuits.A procedure is presented firstly to make compare vectors between pseudorandom test patts by adding some circuits to the original LFSR and secondly to insert some vectors between two successive pseudorandom test patts according to the ordinal selection of every two bits of the compare vector.Then the changes between any successive test patts of the test set generated by the Lppe-TPG are not more than twice.This leads to a decrease of the weighted switching activity(WSA)of the circuit under test(CUT)and therefore a reduction of the power consumption.Experimental results based on some isCAS’85 benchmark circuits show that the peak power consumption has been reduced by 25.25% to 64.46%.Also.the effectiveness of our approach to reduce the total and average power consumption is kept,without losing stuck-at tault coverage.