一种基于自偏置技术的低功耗锁相环设计

• 作 者: 范昊 黄鲁 胡腾飞
• 机 构: 中国科学技术大学电子科学与技术系,
• 出 处: 微电子学
• 发表日期: 2015年02期
• 关键词: PLL Self-biased Charge pump Voltage controlled oscillator

采用TSMC 0.13μm CMOS工艺,设计并实现了一种低功耗、具有固定的环路带宽与工作频率之比,以及良好相位噪声性能的自偏置锁相环(PLL)芯片电路。仿真结果表明,该PLL电路工作频率范围为200~800 MHz,在480MHz输出频率的相位噪声为-108dBc@1 MHz,1.2V电源供电下消耗功耗2mW。芯片核心电路面积仅为0.15mm2,非常适合应用于系统集成。

A TSMC 0.13μm CMOS process is used to design and implement a self-bias PLL circuit with low power consumption, fixed loop bandwidth and operating frequency, and good phase noise performance. The simulation results show that the operating frequency range of the PLL circuit is 200-800 MHz, the phase noise of the output frequency at 480 MHz is -108 dBc @ 1 MHz, and the power consumption consumes 2 mW at 1.2 V power supply. Chip core circuit area of ​​only 0.15mm2, ideal for system integration.