论文部分内容阅读
P896底板总线标准现在正由大西洋两岸的IEEE计算机协会和EWICS(工业计算机系统欧洲研究组)联合进行开发。本文首先描述P896对称和紧耦合的多处理器环境,然后指出通过专门总线的特征支持多处理器的运行。尤其在多处理器中,中断概念统一产生新奇的交叉激励方案。任何处理器都有能力发送源激励(立即功能,中断请求或数据字)到其它的处理器或一组处理器(联合),或者到整个系统。本文还描述把全部处理器链接起来,并以10mb/s的速率传送激励的串行总线。
The P896 backplane bus standard is being developed jointly by the IEEE Computer Society and the EWICS (Industrial Computer Systems Europe Study Group) across the Atlantic. This article first describes the P896 symmetric and tightly coupled multiprocessor environment, and then points out that multiprocessor operations are supported by specialized bus features. Especially in multiprocessors, the concept of interrupts unifies to create novel cross-incentive schemes. Any processor has the ability to send source stimuli (immediate functions, interrupt requests, or data words) to other processors or a group of processors (federation) or to the entire system. This article also describes a serial bus that links all processors and delivers stimulus at a rate of 10 mb / s.