A 83 GHz InP DHBT static frequency divider

• 作 者: 张有涛 李晓鹏 张敏 程伟 陈新宇
• 机 构: National Key Laboratory of Monolithic Integrated Circuits and Modules, Nanjing Electronic Devices In
• 出 处: Journal of Semiconductors
• 发表日期: 2014年04期
• 关键词: peaking maximize topology apart offset dissipation clock operate characterize ci

A static frequency divider is presented using 0.7 m InP DHBTs with 280 GHz ft/fmax. The divider is based on ECL master–slave D-flip–flop topology with 30 HBTs and 20 resistors with a chip size 0.62 0.65 mm2.The circuits use peaking inductance as apart of the loads to maximize the highest clockrate.Momentum simulation is used to accurately characterize the effect of the clock feedback lines at the W band. Test results show that the divider can operate from 1 GHz up to 83 GHz. Its phase noise is 139 dBc/Hz with 100 kHz offset. The power dissipation of divider core is 350 mW.

A static frequency divider is presented using 0.7 m InP DHBTs with 280 GHz ft / fmax. The divider is based on ECL master-slave D-flip-flop topology with 30 HBTs and 20 resistors with a chip size 0.62 0.65 mm2. The circuits use peaking inductance as apart of the loads to maximize the highest clockrate. Momentum simulation is used to accurately characterize the effect of the clock feedback lines at the W band. Test results show that the divider can operate from 1 GHz up to 83 GHz. Its Phase The noise is 139 dBc / Hz with 100 kHz offset. The power dissipation of divider core is 350 mW.