Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonv

• 作 者: 于杰 陈坤基 马忠元 张鑫鑫 江小帆 吴仰晴 黄信凡 Shunri Oda
• 机 构: State Key Laboratory of Solid State Microstructures and School of Electronic Science and Engineering
• 出 处: Chinese Physics B
• 发表日期: 2016年09期
• 关键词: charging erase retention scaling faster areal stored floating systematically com

Based on the charge storage mode,it is important to investigate the scaling dependence of memory performance in silicon nanocrystal(Si-NC) nonvolatile memory(NVM) devices for its scaling down limit.In this work,we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor(CMOS) technology.It is found that the memory windows of eight kinds of test key cells are almost the same of about1.64 V @ ±7 V/1 ms,which are independent of the gate area,but mainly determined by the average size(12 nm) and areal density(1.8×10~(11)/cm~2) of Si-NCs.The program/erase(P/E) speed characteristics are almost independent of gate widths and lengths.However,the erase speed is faster than the program speed of test key cells,which is due to the different charging behaviors between electrons and holes during the operation processes.Furthermore,the data retention characteristic is also independent of the gate area.Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration.

Based on the charge storage mode, it is important to investigate the scaling dependence of memory performance in silicon nanocrystal (Si-NC) nonvolatile memory (NVM) devices for its scaling down limit. In this work, we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor (CMOS) technology. It is found that the memory windows of eight kinds of test key cells are almost the same of about 1.64 V @ ± 7 V / 1 ms , which are independent of the gate area, but mainly determined by the average size (12 nm) and areal density (1.8 × 10-11 / cm ~ 2) of Si-NCs.The program / erase speed characteristics are almost independent of gate widths and lengths.However, the erase speed is faster than the program speed of test key cells, which is due to the different charging behaviors between electrons and holes during the operation processes. is also independent of the gate area. Our findings are useful f or further scaling down of Si-NC NVM devices to improve the performance and on-chip integration.