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To improve the reliability of spaceborne electronic systems,a fault-tolerant strategy of selective triple modular redundancy(STMR)based on multi-objective optimization and evolvable hardware(EHW)against single-event upsets(SEUs)for circuits implemented on field programmable gate arrays(FPGAs)based on static random access memory(SRAM)is presented in this paper.Various topologies of circuit with the same functionality are evolved using EHW firstly.Then the SEU-sensitive gates of each circuit are identified using signal probabilities of all the lines in it,and each circuit is hardened against SEUs by selectively applying triple modular redundancy(TMR)to these SEU-sensitive gates.Afterward,each circuit hardened has been evaluated by SEU Simulation,and the multi-objective optimization technology is introduced to optimize the area overhead and the number of functional errors of all the circuits.The proposed fault-tolerant strategy is tested on four circuits from microelectronics center of North Carolina(MCNC)benchmark suite.The experimental results show that it can generate innovative trade-off solutions to compromise between hardware resource consumption and system reliability.The maximum savings in the area overhead of the STMR circuit over the full TMR design is 58%with the same SEU immunity.
To improve the reliability of spaceborne electronic systems, a fault-tolerant strategy of selective triple modular redundancy (STMR) based on multi-objective optimization and evolvable hardware (EHW) against single-event upsets (SEUs) for circuits implemented on field programmable gate arrays (FPGAs) based on static random access memory (SRAM) is presented in this paper. Verious topologies of circuits with the same functionality are evolved using EHW first. The the SEU-sensitive gates of each circuit are identified using signal probabilities of all the lines in it, and each circuit is hardened against SEUs by selective applying triple modular redundancy (TMR) to these SEU-sensitive gates. Afterward, each circuit hardened has been evaluated by SEU Simulation, and the multi-objective optimization technology introduced to optimize the area overhead and the number of functional errors of all the circuits. The proposed fault-tolerant strategy is tested on four circuits from microelectronics center of No rth Carolina (MCNC) benchmark suite. The experimental results show that it can generate innovative trade-off solutions to compromise between hardware resource consumption and system reliability. The maximum savings in the area overhead of the STMR circuit over the full TMR design is 58% with the same SEU immunity.