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SoC designs that target data center applications,such as networking and storage,uses massive SerDes lanes to achieve high bandwidth and high performance.The high complexity design,which features a large amount of high-speed IP integration,makes power integrity of the whole system a major challenge.Power consumption and simultaneous peak current are high enough to cause large voltage drops and makes design closure difficult,given the demanding minimization of on-die voltage variation.This presentation shares GUC design experience and solutions that ensure power integrity through chip-package co-design,power domain planning,accurate package and IP modeling,and efficient tim-ing sign-off with voltage variation consideration.High-speed IP design quality,modeling,and the physical floor-planning and thorough verification in SoC design integration will also be presented.