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We introduce a method to fabricate solid-state nanopores at sub-20 nm diameter in membranes with embedded metal electrodes across a 200 mm wafer with CMOS compatible semiconductor processes.Multi-layer (metal-dielectric) structures embedded in membranes were demonstrated with high uniformity (± 0.5 nm) across the wafer.Arrays of nanopores were fabricated with average size of 18 ± 2 nm in diameter using a Reactive Ion Etching (RIE) method in lieu of TEM drilling.