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To satisfy the design requirements of analog-to-digital converter(ADC)of high speed sampling system in an infrared focal plane array tester with 1024×1024 pixels,a first inter-stage amplifier of 12-bit 40-Msample/s pipelined ADC was designed with 0.35 μm CMOS technology.On the basis of traditional two-stage amplifier,the cross-coupled class AB output stage and cascode compensation were adopted to improve the output voltage swing and bandwidth.Power dissipation was optimized with math tools.Circuit and layout design were completed.Simulation results show that the designed amplifier has good performance of 95 dB dc gain,±2 V output voltage swing,190 MHz bandwidth and 63° phase margin with feedback factor 1/4,33 mW power dissipation and so on,which can meet the system requirements.
To satisfy the design requirements of analog-to-digital converter (ADC) of high speed sampling system in an infrared focal plane array tester with 1024 × 1024 pixels, a first inter-stage amplifier of 12-bit 40-Msample / s pipelined ADC was designed with 0.35 μm CMOS technology. On the basis of traditional two-stage amplifier, the cross-coupled class AB output stage and cascode compensation were adapted to improve the output voltage swing and bandwidth. Power dissipation was optimized with math tools. Circuit and layout design were completed. Simulation results show that the designed amplifier has good performance of 95 dB dc gain, ± 2 V output voltage swing, 190 MHz bandwidth and 63 ° phase margin with feedback factor 1 / 4,33 mW power dissipation and so on , which can meet the system requirements.