论文部分内容阅读
讨论了用横向pnp晶体管作电流源,多收集极npn晶体管作反相器的集成注入逻辑(I~2L),或称并合晶体管逻辑(MTL)。对五级闭环反相器链测得的速度-功率乘积为每门0.13微微焦耳,封裝密度达400门/毫米~2。与MOS逻辑的版图设计进行了比较。提出了制造较高速电路的可行方法。
Discussed the integrated injection logic (I ~ 2L), or the merge transistor logic (MTL), which uses a lateral pnp transistor as a current source and a multi-collector npn transistor as an inverter. The speed-power product measured for a five-stage closed-loop inverter chain is 0.13 pico-joules per gate with a packing density of 400 gates / millimeter-2. Compared with MOS logic layout design. A feasible method of manufacturing higher speed circuits is proposed.