A low-power time-domain VCO-based ADC in 65 nm CMOS

• 作 者: 王陈銮 刁盛锡 林福江
• 机 构: Department of Electronic Science & Technology University of Science and Technology of China,
• 出 处: Journal of Semiconductors
• 发表日期: 2014年10期
• 关键词: oscillator cancellation modulator shaping consuming converter convert analog fig

A low-power, high-Fo M(figure of merit), time-domain VCO(voltage controlled oscillator)-based ADC(analog-to-digital converter) in 65 nm CMOS technology is proposed. An asynchronous sigma–delta modulator(ASDM) is used to convert the voltage input signal to a square wave time signal, where the information is contained in its pulse-width. A time-domain quantizer, which uses VCO to convert voltage to frequency, is adopted, while the XOR(exclusive-OR) gate circuits convert the frequency information to digital representatives. The ASDM does not need an external clock, so there is no quantization noise. At the same time, the ASDM applies a harmonicdistortion-cancellation technique to its transconductance stage, which increases the SNDR(signal to noise and distortion ratio) performance of the ASDM. Since the output of the ASDM is a two-level voltage signal, the VCO’s V–F(voltage to frequency)conversion curve is always linear. The XOR phase quantizer has an inherent feature of first-order noise-shaping. It puts the ADC’s low-frequency output noise to high-frequency which is further filtered out by a low-pass filter. The proposed ADC achieves an SNR/SNDR of 54. d B/54.3 d B in the 8 MHz bandwidth,while consuming 2.8 m W. The Fo M of the proposed ADC is a 334 f J/conv-step.

A low-power, high-Fo M figure of merit, time-domain VCO (voltage controlled oscillator) -based ADC (analog-to-digital converter) AS time-domain quantizer, which uses VCO to convert voltage to frequency, is adopted, while the XOR (eg, ASOR) is used to convert the voltage input signal to a square wave time signal, where the information is contained in its pulse- exclusive-OR) gate circuits convert the frequency information to digital representatives. which ASDM does not need an external clock, so there is no quantization noise. the SNDR (signal to noise and distortion ratio) performance of the ASDM. Since the output of the ASDM is a two-level voltage signal, the VCO’s V-F (voltage to frequency) conversion curve is always linear. an inherent feature of first-order n It puts the ADC’s low-frequency output noise to high-frequency which is further filtered out by a low-pass filter. The proposed ADC achieves an SNR / SNDR of 54. d B / 54.3 d B in the 8 MHz bandwidth, while consuming 2.8 m W. The Fo M of the proposed ADC is a 334 f J / conv-step.