采用相邻采样求和的突发模式相位插值型CDR

• 作 者: 覃林 黄鲁 傅忠谦
• 机 构: 中国科学技术大学电子科学与技术系,
• 出 处: 微电子学
• 发表日期: 2016年02期
• 关键词: Clock and data recovery(CDR) Burst mode(BM) Phase interpolator(PI) CMOS

提出了一种具有良好抑制输入数据抖动性能的突发模式相位插值型时钟数据恢复电路。在传统相位插值型电路结构的基础上,在采样保持电路与相位插值电路之间加入一级求和电路,理论分析和仿真结果表明,恢复时钟相位变化受输入数据抖动的影响明显减小。电路基于1.1 V SMIC 40nm 1P8M CMOS工艺搭建,其数据率为6.25Gb/s,消耗功耗为6.7 mW,版图面积为0.35mm~2。

A burst-mode phase-interpolated clock data recovery circuit with good jitter suppression of input data is proposed. Based on the traditional phase-interpolating circuit structure, a first-order summing circuit is added between the sample-and-hold circuit and the phase interpolation circuit. The theoretical analysis and simulation results show that the change of the recovery clock phase is significantly reduced by the jitter of the input data. The circuit is based on a 1.1 V SMIC 40nm 1P8M CMOS process with a data rate of 6.25Gb / s, a power consumption of 6.7mW, and a layout area of ​​0.35mm ~ 2.