TIMING SLACK OPTIMIZATION APPROACH USING FPGA HYBRID ROUTING STRATEGY OF RIP-UP-RETRY AND PATHFINDE

• 作 者: Yu Wei Yang Haigang Liu Yang H
• 机 构: InstituteofElectronics,UniversityofChineseAcademyofSciences
• 出 处: 电子科学学刊：英文版
• 发表日期: 2014年3期
• 基金项目: Supported by National High Technology Research and Develop Program of China （No. 2012AA012301） and the CAS/SAFEA International Partnership Program for Creative Research Teams.

To improve the path slack of Field Programmable Gate Array(FPGA), this paper proposes a timing slack optimization approach which utilizes the hybrid routing strategy of rip-up-retry and pathfinder. Firstly, effect of process variations on path slack is an