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为了获得低功耗性能,将时钟CMOS电路用于读放电路和位线负载电路。六管单元和特别的读出放大器,使器件能在2.5V下稳定工作。该电路的另一别点是和TTL及I~2L电路相容。采用了N阱CMOS工艺,理由是:(1)N阱CMOS工艺和NMOS工艺相容;(2)在CMOS存贮器中,大约70%左右的器件是NMOS器件,因此,N阱CMOS工艺能保持在高阻衬底上制备高性能NMOS电路的优点,更充分发挥NMOS的优势.和P阱比较,阱的面积也大大减小了.采用了3μm的设计规则.为了保持两种器件有效沟道长度的平衡,两种器件的设计沟道长度分别为3μm和3.5μm,存贮单元面积为43×51μm.
For low power consumption, clock CMOS circuits are used for read and bit line load circuits. Six-pipe unit and a special sense amplifier, the device can be stable at 2.5V work. Another point of this circuit is TTL and I ~ 2L circuit compatible. The N-well CMOS process is used for the following reasons: (1) N-well CMOS process is compatible with NMOS process; and (2) about 70% of CMOS devices are NMOS devices in CMOS memory. Therefore, Maintaining the advantages of high performance NMOS circuits on high-resistance substrates and taking full advantage of the advantages of NMOS, the well area is greatly reduced compared to the P-wells. A 3μm design rule was used. In order to maintain the effective ditch The length of the channel is balanced. The designed channel lengths of the two devices are 3 μm and 3.5 μm, respectively, and the memory cell area is 43 × 51 μm.