论文部分内容阅读
对于多处理器计算机—SIMD 和 MIMD—的互连网络是本文讨论的主题。这将包括它们的结构,包交换开关和线路交换开关的控制和实现。论题还包括单级网络和多级网络及其内外部的排队问题。本文还阐明了包交换开头从 O(LogN)到 O(N)的硬件构成以及用来实现任意交换的从 O(LogN)到 O(N)的硬件。
For multi-processor computers - SIMD and MIMD - the interconnection network is the subject of this article. This will include their structure, packet switch and line switch control and implementation. Topics also include single-level networks and multi-level networks and their internal and external queuing issues. This article also illustrates the hardware architecture for packet switching from O (LogN) to O (N) at the beginning and hardware from O (LogN) to O (N) for arbitrary exchanges.