An 85mW 14-bit 150MS/s Pipelined ADC with a Merged First and Second MDAC

• 作 者: LI Weitao LI Fule YANG Changyi LI Shengjing WANG Zhihua
• 机 构: Institute of Microelectronics,Tsinghua University,
• 出 处: 中国通信
• 发表日期: 2015年05期
• 关键词: analog-to-digital conversion low power calibration high speed and high resolutio

A low-power 14-bit 150MS/s analog-to-digital converter(ADC) is presented for communication applications.Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted.Opamp and capacitor sharing between the first multiplying digital-to-analog converter(MDAC)and the second one reduces the total opamp power further.The dedicated sample-andhold amplifier(SHA) is removed to lower the power and the noise.The blind calibration of linearity errors is proposed to improve the performance.The prototype ADC is fabricated in a 130 nm CMOS process with a 1.3-V supply voltage.The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input.It consumes 85 mW,which includes 57 mW for the ADC core,11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.

A low-power 14-bit 150 MS / s analog-to-digital converter (ADC) is presented for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp. Opamp and capacitor sharing between the first multiplying digital-to-analog converter (MDAC) and the second one reduces the total opamp power further.The dedicated sample-andhold amplifier (SHA) is removed to lower the power and the noise.The blind calibration of linearity errors is proposed to improve the performance.The prototype ADC is fabricated in a 130 nm CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input.I consumes 85 mW , which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.