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对无线局域网接收机用锁相环型频率综合器的几项关键技术进行了研究.首先分析了锁相环型频率综合器的结构并提出了系统的主要参数.采用TSMC0.18μm射频CMOS工艺设计了一个具有低相位噪声的单片LC调谐型压控振荡器.其在4.189GHz频点上4MHz频偏处所测得的相位噪声为-117dBc/Hz.采用TSMC0.18μm混合信号CMOS工艺实现了具有低功耗的下变频模块电路.该电路在1.8V电源供电下可正常工作,功耗为13mW.
Several key technologies of phase-locked loop frequency synthesizer for wireless local area network receiver are studied.Firstly, the structure of phase-locked loop frequency synthesizer is analyzed and the main parameters of the system are proposed.Using TSMC0.18μm RF CMOS process design A monolithic LC-tuned voltage-controlled oscillator with low phase noise has a phase noise of -117 dBc / Hz measured at 4 MHz offset at 4.189 GHz using a TSMC 0.18 μm mixed-signal CMOS process Downconversion module circuit with low power consumption. The circuit operates at 1.8V power supply and consumes 13mW.