论文部分内容阅读
本文提出一种基于ISP逻辑器件使用逻辑图输入方式设计同步时序逻辑电路的标准形式。该形式电路结构是固定的，根据电路的逻辑功能在相应的输入端填入数据即可。该方法设计过程简单，概念清楚，易于掌握。
In this paper, we propose a standard form for designing synchronous sequential logic circuits based on logic input of logic devices of ISP. The form of the circuit structure is fixed, according to the logical function of the circuit to fill in the corresponding input data can be. The method has simple design process, clear concept and easy to grasp.