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设计了应用于GMSK调制,工作在2·4GHz ,CMOS全差分的∑-△频率综合器.调制器中采用预补偿的分数N锁相环.推导了Ⅱ型三阶锁相环的传输函数,并指出影响环路传输函数的重要参数.介绍了校准重要的环路参数的方法.锁相环设计中采用差分调节的LC压控振荡器和全差分的电荷泵.设计的电路利用0·18μm1P6MCMOS工艺进行仿真.由于锁相环的组成模块中采用了低功耗设计,锁相环的功耗仅为11mW左右,调制器的数据率达到2Mb/s .
A Σ-Δ frequency synthesizer which is applied to GMSK modulation and works at 2.4GHz and CMOS fully differential is designed and the pre-compensated fractional-N phase-locked loop is used in the modulator.The transfer function of type Ⅱ third-order phase-locked loop is deduced, And points out the important parameters that affect the loop transfer function.The method of calibrating the important loop parameters is introduced.The LC voltage controlled oscillator with differential regulation and the fully differential charge pump are used in the PLL design.The circuit is designed by using 0.18μm1P6MCMOS Process simulation.As a result of phase-locked loop module used in the design of low-power, phase-locked loop power consumption is only about 11mW, the modulator data rate of 2Mb / s.