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本文讨论了并行位选MOS存贮器的设计方案。用LSI技术能获得40K位的存贮容量,用字专和存贮字数都能扩大存贮容量。存贮器的实际体积较之用磁芯设计的体积要小得多。每位功耗同样比用磁芯的要小,全周期为1MS甚至更小,每位成本与磁芯设计成本进行了有利地比较。术语索引:地址选择技术,芯片互连的（?）虑,扇出的考虑,输入输出和地址寄存器,存贮器与计算机接口的实现,多层处理增速和减小单元尺寸,存贮器芯片的晶体管和导线数量,存贮芯片的结构,存贮芯片的输出逻辑,解决扇出问题,存贮器芯片的总数等等。
This article discusses the design of parallel bit-selected MOS memory. With LSI technology can get 40K-bit storage capacity, with words and store words can expand the storage capacity. The actual size of the memory is much smaller than the size of the core design. Each power consumption is also smaller than the core, the whole cycle is 1MS or less, each cost is compared with the core design costs were compared. Glossary of Terms: Address Selection Technology, Chip Interconnect Considerations, Fanout Considerations, I / O and Address Registers, Memory and Computer Interface Implementation, Multi-Processing Growth and Cell Size Reduction, Memory The number of transistors and wires in the chip, the structure of the memory chip, the output logic of the memory chip, the problem of fanout, the total number of memory chips, and the like.