Low Power Design of Pipelined ADC for Power Line Baseband Communication

• 作 者: 陈洋 Xuejing Liu Mengmeng Fang Pingfen Lin
• 机 构: Beijing Embedded System Key Lab,Beijing University of Technology,
• 出 处: 电子世界
• 发表日期: 2013年04期
• 关键词: SFDR switch converter analog capacitor transceiver calibration mirror Capacitor

This paper presents a 10bit 5MS/s pipelined analog-to-digital converter(ADC)for single carrier power line communication transceiver.It’s a low-power method by using switched op amp technique,and proposes the switch capacitor(SC)bias circuitry to solve the startup issue of the current bias.Two common-mode feedback networks are employed to solve the problem of common-mode stability.Removes the sample and hold circuitry(SHA)to further reduce power consumption.Simulation result shows that the proposed ADC achieves 9.6 ENOB,75.8dB SFDR.The power consumption is 0.6 mA for 1.8V supply voltage. Index Terms:Pipelined ADC;switched op amp;switch capacitor bias;SHA-less

This paper presents a 10bit 5MS / s pipelined analog-to-digital converter (ADC) for single carrier power line communication transceiver. It’s a low-power method by using switched op amp technique, and proposes the switch capacitor (SC) bias circuitry to solve the startup issue of the current bias. Two common-mode feedback networks are employed to solve the problem of common-mode stability. Demoves the sample and hold circuitry (SHA) to further reduce power consumption. Simulation result shows that that proposed ADC achieves 9.6 ENOB, 75.8dB SFDR.The power consumption is 0.6 mA for 1.8V supply voltage. Index Terms: Pipelined ADC; switched op amp; switch capacitor bias; SHA-less