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A differential automatic gain control(AGC) circuit is presented.The AGC architecture contains twostage variable gain amplifiers(VGAs) which are implemented with a Gilbert cell,a peak detector(PD),a low pass filter,an operational amplifier,and two voltage to current(V-I) convenors.One stage VGA achieves 30 dB gain due to the use of active load.The AGC circuit is implemented in UMC 0.18-μm single-poly six-metal CMOS process technology.Measurement results show that the final differential output swing of the 2nd stage VGA is about 0.9-Vpp;the total gain of the two VGAs can be varied linearly from -10 to 50 dB when the control voltage varies from 0.3 to 0.9 V.The final circuit(containing output buffers and a band-gap reference) consumes 37 mA from single 1.8 V voltage supply.For a 50 mV amplitude 60%modulation depth input AM signal it needs 100μs to stabilize the output.The frequency response of the circuit has almost a constant -3 dB bandwidth of 2.2 MHz. Its OIP3 result is at 19 dBm.
A differential automatic gain control (AGC) circuit is presented. The AGC architecture contains twostage variable gain amplifiers (VGAs) which are implemented with a Gilbert cell, a peak detector (PD), a low pass filter, an operational amplifier, and two voltage to current (VI) convenors. One stage VGA achieves 30 dB gain due to the use of active load. The AGC circuit is implemented in UMC 0.18-μm single-poly six-metal CMOS process technology. Measurement results show that the final differential output swing of the 2nd stage VGA is about 0.9-Vpp; the total gain of the two VGAs can be varied linearly from -10 to 50 dB when the control voltage varies from 0.3 to 0.9 V. The final circuit (containing output buffers and a band -gap reference) consumes 37 mA from single 1.8 V voltage supply. For a 50 mV amplitude 60% modulation depth input AM signal it needs 100 μs to stabilize the output. The frequency response of the circuit has almost a constant -3 dB bandwidth of 2.2 MHz. Its OIP3 result is at 19 dBm.