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This paper presents a low power,area-efficient and radiation-hardened 12-bit 1 MS/s successive approximation register(SAR) analog-to-digital converter(ADC) for multi-channel CdZnTe(CZT) detector applications.In order to improve the SAR-ADC’s accuracy,a novel comparator is proposed in which the offset voltage is selfcalibrated and also a new architecture for the unit capacitor array is proposed to reduce the capacitance mismatches in the charge-redistribution DAC.The ability to radiation-harden the SAR-ADC is enhanced through circuit and layout design technologies.The prototype chip was fabricated using a TSMC 0.35 μm 2P4 M CMOS process.At a3.3/5 V power supply and a sampling rate of 1 MS/s,the proposed SAR-ADC achieves a peak signal to noise and distortion ratio(SINAD) of 67.64 dB and consumes only 10 mW power.The core of the prototype chip occupies an active area of 1180×1080 μm~2.
This paper presents a low power, area-efficient and radiation-hardened 12-bit 1 MS / s successive approximation register (SAR) analog to digital converter (ADC) for multi-channel CdZnTe (CZT) improve the SAR-ADC’s accuracy, a novel comparator is proposed in which the offset voltage is selfcalibrated and also a new architecture for the unit capacitor array is proposed to reduce the capacitance mismatches in the charge-redistribution DAC. ability to radiation-harden the SAR-ADC is enhanced through circuit and layout design technologies. The prototype chip was fabricated using a TSMC 0.35 μm 2P4 M CMOS process. At3.3 / 5 V power supply and a sampling rate of 1 MS / s, the proposed SAR- The ADC achieves a peak signal to noise and distortion ratio (SINAD) of 67.64 dB and consumes only 10 mW power. The core of the prototype chip occupies an active area of 1180 × 1080 μm ~ 2.