基于NIOS Ⅱ的FPGA配置技术

• 作 者: 余金磊 孙明杰
• 机 构: 中国电子科技集团公司第五十四研究所,
• 出 处: 无线电通信技术
• 发表日期: 2013年03期
• 关键词: 现场可编程门阵列 配置数据更新 嵌入式 串行存储

针对电子设备中现场可编程门阵列(FPGA)大量使用所带来的FPGA配置数据更新的需求,提出了一种基于嵌入式的多片FPGA配置数据更新技术。通过在FPGA内嵌入NIOS II软核处理器来识别外部发送的配置数据,读写本地EPCS存储器,实现配置数据的更新。详细论述了使用Quartus II SOPC Builder与Nios II 9.0 IDE进行软硬件设计的过程,并与传统的FPGA配置方法进行了对比测试。测试结果表明这种技术应用更加灵活,效率高,易于在工程实际中实现。

In order to meet the demand of FPGA configuration data updating caused by the extensive use of field programmable gate arrays (FPGAs) in electronic devices, an embedded multi-chip FPGA configuration data updating technology is proposed. By embedded in the FPGA NIOS II soft-core processor to identify the external sent configuration data, read and write local EPCS memory, to achieve the configuration data update. The process of hardware and software design using Quartus II SOPC Builder and Nios II 9.0 IDE is discussed in detail, and compared with the traditional FPGA configuration method. The test results show that the application of this technique is more flexible, efficient and easy to implement in engineering practice.