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本文描述了用于双极集成电路制造的氧化物隔离等平面Ⅰ工艺过程。隔离氧化是用Si_3N_4膜掩蔽、由低温、高压水汽氧化实现的。为解决很薄的外延层及开槽氧化所带来的困难提出了一系列措施,使氧化物隔离等平面工艺成功地应用于全温度、全电压补偿的ECL100K系列和LSTTL系列集成电路的研制中,获得了预期的性能改善。
This article describes Planar I processes for oxide isolation and the like used in the fabrication of bipolar integrated circuits. Isolation oxidation is masked with Si_3N_4 film, by low temperature, high pressure water vapor oxidation achieved. A series of measures are put forward to solve the problems caused by very thin epitaxial layer and slotted oxidation. The planarization process such as oxide isolation is successfully applied to the development of full temperature and voltage compensated ECL100K series and LSTTL series integrated circuits , The expected performance improvement was achieved.