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针对系统对于SDH性能告警处理方面的需求,利用Altera低成本的FPGA开发设计了基于NiosⅡ嵌入式CPU的处理平台,利用SOPC Builder创建了NiosⅡ SoC硬件系统,开发了嵌入式软件,从而实现对外围ASIC芯片的配置和性能告警处理算法。
According to the demand of the system for the SDH performance alarm processing, a Nios Ⅱ embedded CPU processing platform is designed and developed by using Altera low-cost FPGA. NiosⅡ SoC hardware system is created by using SOPC Builder, and embedded software is developed to realize peripheral ASIC Chip configuration and performance alarm processing algorithm.