Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits

• 作 者: Omnia S. Ahmed Mohamed F. Abu-
• 机 构: CollegeofComputingandInformationTechnology,ElectronicsEngineeringDepartment,FacultyofEngineering,Rad
• 出 处: 电路与系统(英文)
• 发表日期: 2013年3期
• 关键词: Dynamic Power ESTIMATION LOGIC PICTURES CMOS Digital LOGIC Circuits TOGGLE Rate

In this research, a fast methodology to calculate the exact value of the average dynamic power consumption for CMOS combinational logic circuits is developed. The delay model used is the unit-delay model where all gates have the same propagation delay. Th