论文部分内容阅读
提出了一种可用组合逻辑实现的准浮点计算方法。组合逻辑不需要时钟，能完成高速实时数据运算．这是一种近似计算，可完成复数求模等非线性运算．准浮点运算电路由数据调理单元、组合逻辑运算单元以及定点恢复单元组成．本文分析了准浮点计算方法的误差．如果数据长度保留８位，则由准浮点计算方法导致的相对误差小于０．０１．
A quasi-floating-point calculation method that can be implemented by combinatorial logic is proposed. Combinatorial logic does not require a clock, to complete high-speed real-time data operations. This is an approximate calculation that can perform complex calculations such as nonlinear operations. Quasi-floating-point operation circuit consists of data conditioning unit, combinational logic unit and fixed-point recovery unit. This article analyzes the error of quasi-floating point calculation method. If the data length is reserved for 8 bits, the relative error due to quasi-floating-point calculation is less than 0.01.