LSB page refresh based retention error recovery scheme for MLC NAND Flash

• 作 者: Haozhi MA Lifang LIU Liyang PAN Jun XU
• 机 构: Institute of Microelectronics, Tsinghua University,Tsinghua National Laboratory for Information Scie
• 出 处: Science China(Information Sciences)
• 发表日期: 2016年04期
• 关键词: retention NAND floating inevitable overhead compensate cycled hardware blocks sc

NAND Flash memories present inevitable decline in reliability due to scaling down and multilevel cell(MLC) technology. High retention error rate in highly program/erase(P/E) cycled blocks induces stronger ECC requirement in system, causing higher spare bits cost and hardware overhead. In this paper, a least significant bit(LSB) page refresh based retention recovery scheme is proposed to improve the retention reliability of highly scaled MLC NAND Flash. As in the scheme, LSB page refresh operation induces floating gate electron re-injection to compensate charge leakage during long retention time, and realizes retention error rate reduction. Experiment result on 2x-nm MLC NAND Flash exhibits more than 78% retention error rate reduction. Compared with reported retention error recovery scheme, the proposed scheme presents 2.5 times recovery efficiency promotion and 60% latency reduction.

NAND Flash memories present inevitable decline in reliability due to scaling down and multilevel cell (MLC) technology. High retention error rate in highly program / erase (P / E) cycled blocks induces stronger ECC requirement in system, causing higher spare bits cost and hardware Over this paper, a least significant bit (LSB) page refresh based retention recovery scheme is proposed to improve the retention reliability of highly scaled MLC NAND Flash. As in the scheme, LSB page refresh operation induces floating gate electron re-injection to Compared with reported retention error recovery scheme, the proposed scheme presents 2.5 times recovery efficiency promotion and 60% latency reduction.