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针对多正则表达式匹配已经成为制约网络安全系统性能瓶颈的问题,提出一种硬件四级流水线的多正则表达式匹配结构。该结构对多条正则表达式统一处理,将正则表达式切割成字符串和循环控制,采用字符串匹配结构处理字符串,并设计专用硬件电路处理循环限制。实验表明,该硬件结构在Virtex2和Virtex4 FPGA上分别可以达到1.9和2.1Gb/s的匹配性能,与国外相关研究成果相比,消耗更少的存储空间,并支持更多的正则表达式。
For multi-regular expression matching has become a bottleneck restricting the performance of network security system, a multi-regular expression matching structure of hardware four-level pipeline is proposed. The structure of a number of regular expressions unified treatment, the regular expression will be cut into strings and loop control, the string matching structure to deal with strings, and design a dedicated hardware circuit processing cycle restrictions. Experiments show that this hardware architecture achieves 1.9 and 2.1 Gb / s matching performance on Virtex2 and Virtex4 FPGAs, respectively, which consumes less storage space and supports more regular expressions than other related research results.