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国际半导体技术发展路线工作组确定了把套刻控制作为65nm及其以下的技术节点未知解决方法的技术障碍。最严重的问题是总的测量方法不确定、CMP工艺的坚固性以及器件的相互关系。系统的根源引起的图形位置误差(PPE)分析在摩托罗拉公司的DanNoble中心已得到确定,即目前传统的框中框式套刻标记在所有的三种类型引起了缺陷。一种先进的利用成像标记的建议是基于栅格型且能被分割成类似于器件图形的特征图形。在采用193nm光刻设备进行多浅沟道隔离图形套刻的情况下,这种标记显示出将总的测量方法不确定因素减少了40%。
The International Working Group on the Technology Roadmap for Semiconductors identified technical hurdles to using overlay control as an unknown solution to technology nodes 65nm and below. The most serious problems are the uncertainty of the overall measurement method, the robustness of the CMP process, and the interdependencies of the devices. The Graphical Position Error Analysis (PPE) analysis caused by the system’s root cause has been identified at the Motorola DanNoble Center, where the conventional box-in-box markings cause defects in all three types. An advanced proposal for using imaging markers is based on a grid and can be segmented into feature graphics similar to device graphics. With 193nm lithography equipment for multi-shallow trench isolation patterning, this mark shows a 40% reduction in the overall measurement uncertainty.