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为了提高乘法器的综合性能,提出了一种新的冗余Booth三阶算法和跳跃式Wallace树结构,前者可以减少部分积的数目,提高部分积的产生速度,后者可以加快部分积的压缩,减少电路内部的伪翻转,从而降低功耗.基于冗余Booth三阶算法和跳跃式Wallace树结构,采用0.25μmCMOS工艺,实现了54×54位全定制乘法器,其乘法延时为4.3 ns,芯片面积为1.38 mm2,50MHz频率下的动态功耗仅为47.2 mW.模拟验证表明,与采用传统Wallace树结构和改进Booth二阶算法的乘法器相比,该乘法器的乘法延时减少了23%,功耗降低了17%,面积减少了20%.
In order to improve the overall performance of the multiplier, a new redundant Booth third-order algorithm and skip Wallace tree structure are proposed. The former can reduce the number of partial products and increase the generation speed of partial products, which can speed up the compression of partial products , Reducing the internal flip-flop, thereby reducing power consumption.Based on the redundant Booth third-order algorithm and the hop-Wallace tree structure, a 54 × 54-bit full custom multiplier is implemented with a 0.25μm CMOS process with a multiplication delay of 4.3 ns With a chip area of 1.38 mm2 and a dynamic power dissipation of only 47.2 mW at 50 MHz.Model verification shows that the multiplier delay of this multiplier is reduced compared to a multiplier using a traditional Wallace tree structure and an improved Booth second order algorithm 23%, a 17% reduction in power consumption and a 20% reduction in area.