A low reference spur quadrature phase-locked loop for UWB systems

• 作 者: 傅海鹏 蔡德鋆 任俊彦 李巍 李宁
• 机 构: State Key Laboratory of ASIC & System,Fudan University,Micro-/Nano-Electronics Science and Technolog
• 出 处: 半导体学报
• 发表日期: 2011年11期
• 关键词: quadrature locked synthesizer oscillator offset guaranteed operated operate supp

This paper presents a low phase noise and low reference spur quadrature phase-locked loop(QPLL) circuit that is implemented as a part of a frequency synthesizer for China UWB standard systems.A glitch-suppressed charge pump(CP) is employed for reference spur reduction.By forcing the phase frequency detector and CP to operate in a linear region of its transfer function,the linearity of the QPLL is further improved.With the proposed series-quadrature voltage-controlled oscillator,the phase accuracy of the QPLL is guaranteed.The circuit is fabricated in the TSMC 0.13μm CMOS process and operated at 1.2-V supply voltage.The QPLL measures a phase noise of -95 dBc/Hz at 100-kHz offset and a reference spur of -71 dBc.The fully-integrated QPLL dissipates a current of 13 mA.

This paper presents a low phase noise and low reference spur quadrature phase-locked loop (QPLL) circuit that is implemented as a part of a frequency synthesizer for China UWB standard systems. A glitch-suppressed charge pump (CP) is employed for reference spur reduction.By forcing the phase frequency detector and CP to operate in a linear region of its transfer function, the linearity of the QPLL is further improved. Due to the proposed series-quadrature voltage-controlled oscillator, the phase accuracy of the QPLL is guaranteed. The circuit is fabricated in the TSMC 0.13 μm CMOS process and operated at 1.2-V supply voltage. The QPLL measures a phase noise of -95 dBc / Hz at 100-kHz offset and a reference spur of -71 dBc. The fully-integrated QPLL dissipates a current of 13 mA.