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LD-CELP可以全面满足16Kbps算法的性能要求,已被广泛应用在会议电视系统、IP电话等领域。基于此规范,采用Verilog HDL硬件描述语言完成RTL级设计,所有编解码结构都由Verilog实现的DSP engine完成,并对最佳码书序号进行了压缩处理,解决了最佳码书序号的比特浪费问题。FPGA实现采用Xilinx公司的XC3S1000芯片。验证结果表明,系统功能完全正确,符合协议要求。
LD-CELP can fully meet the performance requirements of the 16Kbps algorithm and has been widely used in the fields of conference and TV systems and IP telephones. Based on this specification, the Verilog HDL hardware description language is used to complete the RTL level design. All the codec structures are completed by the Verilog DSP engine, and the best codebook number is compressed to solve the bit waste of the best codebook number problem. FPGA using Xilinx XC3S1000 chip. Verification results show that the system functions completely correct, in line with the agreement.