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我们提出了一种垂直双扩散功率MOS(VDMOS)晶体管的导通电阻模型,着重于讨论单元版图的优化设计和验证实验数据。采用六种不同的网格状单元图形(包括正方形单元和六角形单元)中的任何一种结构,基本上都能得到同样的最小导通电阻R_(ono)特别是当各单元的p阱宽度相同且阱的面积与单元面积之比也相同时,各种网格状单元图形的导通电阻差不多是完全相同的。除非通过巧妙的设计使条状单元的阱的宽度比网格状单元的小1.6倍,否则在一般情况下,网格状单元的R_(on)比条状的低,我们用设计例子和实验来说明简单的优化步骤,首先选择与生产工艺相适应的最小的p阱宽度和深度,然后找出p阱间的最佳间隔距离。
We propose an on-resistance model for a vertical double diffused power MOS (VDMOS) transistor, focusing on the optimal layout of the cell layout and verifying the experimental data. Using any one of six different grid cell patterns (including square and hexagonal cells), basically the same minimum on-resistance, R on (ono) can be obtained, especially when the p-well width of each cell When the same area ratio of the wells to the cell area is also the same, the on-state resistances of the various grid-like cell patterns are almost the same. Unless the width of the well of the stripe cell is 1.6 times smaller than the size of the cell by clever design, in general the R_ (on) of the cell in the stripe is lower than that of the stripe. We use design examples and experiments To illustrate simple optimization steps, first select the smallest p-well width and depth appropriate to the manufacturing process and then find the best separation distance between p-wells.