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机械设计人员和LSI设计人员减小漏电流的对策,主要针对亚阈值漏电流。但是,对于65nm及以下的工艺,栅漏电流将使机械设计人员和LSI设计人员面临更大挑战。随着微细化的发展,栅漏电流的影响将更加显著。原因在于晶体管栅绝缘膜的物理厚度Tox变得太薄所导致的沟道电流,主要是由晶
Mechanical designers and LSI designers to reduce leakage of countermeasures, mainly for sub-threshold leakage current. However, for 65nm and below process, gate leakage current will be mechanical designers and LSI designers face greater challenges. With the development of miniaturization, the impact of gate leakage will be more significant. The reason is that the channel current caused by the physical thickness Tox of the transistor gate insulating film becoming too thin is mainly caused by the crystal