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本文叙述常规双层多晶硅单管动态RAM单元的结构和工艺,该单元中进行了特殊的器件改进,获得了最佳密度、速度和软误差率(SER)的256K和低成本64K动态RAM产品。通过采用相当于150埃氧化层厚度的薄介质和双场氧化(DFO)工艺减少存贮电容的鸟嘴(<0.2μm),使得单元存贮容量提高。P~-衬底上的P阱对于由入射α粒子所产生电荷提供了反射势垒。低金属字线电容和短的深掺杂扩散位线加快了单元存取时间。研制出了面积为53μm~2到77μm~2的单元,并进行了试验。此工艺应用平行极板等离子体对各层进行腐蚀,在关键掩膜层上采用圆片步进机光刻。此单元结构已被用于芯片面积为154密耳见方,70ns的存取时间和<0.001％/1KHr的软误差率的64K存贮器的设计之中。
This article describes the structure and process of a conventional double-layer polysilicon single-pass dynamic RAM cell with special device improvements and a 256K, low-cost 64K dynamic RAM product with optimized density, speed and soft error rate (SER). The cell storage capacity is improved by reducing the storage capacity of the beak (<0.2 μm) using a thin dielectric equivalent of 150 Å of oxide thickness and a dual field oxide (DFO) process. The P-well on the P ~ substrate provides a reflective barrier to the charge generated by the incident alpha particle. Low metal wordline capacitance and short deep-doped diffused bitlines speed up cell access times. Developed a unit area of 53μm ~ 2 to 77μm ~ 2, and conducted a test. This process uses parallel plate plasma to etch the layers, using wafer stepper lithography on the key mask layers. This cell structure has been used in the design of a 64K memory with a chip area of 154 mils square, an access time of 70 ns, and a soft error rate of <0.001% / 1KHr.