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基于SMIC 0.13μm CMOS工艺,在3.3V/1.2V(模拟/数字)双电源下,设计了一种11位80MS/s的数/模转换器(DAC)。电路采用分段式电流舵结构,高6位为温度计码,低5位为二进制码。该DAC应用于无线通信SoC的模拟前端。IP核尺寸为960μm×740μm,功耗40mW,电路仿真结果显示,DAC的最大积分非线性误差和微分非线性误差分别为0.5LSB和0.3LSB。在20MHz输出信号频率和80MHz采样率下,DAC差分输出的SFDR为80dB。设计的电路已经通过MPW流片验证,给出了DAC芯片照片与实测数据。
Based on the SMIC 0.13μm CMOS process, an 11-bit, 80MS / s DAC is designed with a dual 3.3V / 1.2V (analog / digital) power supply. The circuit adopts segmented current rudder structure, the upper 6 bits are thermometer codes, the lower 5 bits are binary codes. The DAC is used in the analog front end of wireless communication SoCs. The IP core size is 960μm × 740μm and the power dissipation is 40mW. The simulation results show that the maximum integral nonlinearity error and differential nonlinearity error of DAC are 0.5LSB and 0.3LSB, respectively. The SFDR of the DAC differential output is 80dB at 20MHz output signal frequency and 80MHz sample rate. Design of the circuit has been verified by the MPW chip, given the DAC chip photos and measured data.