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伴随高精度电源系统的发展,数字电压调整模块(DVRM)需要高速,高精度的模数转换器.为此,提出了一种新型预放大器链设计方法,能够获得非常小的LSB.该方法优化了预放大器输入管的尺寸,在保证足够小的失调电压的前提下,使各级输入管面积总和最小.为验证该优化方法,结合电阻均衡技术,构造了一个3级结构flash型ADC.与一般设计相比,输入管总面积减少了57%.每个LSB为3.125 mV,直接转换精度3.5 bit,得益于窗口结构,在满度输入范围内等效精度为8 bit,采样率为224 Msample/s.
With the development of high-precision power system, Digital Voltage Regulation Module (DVRM) needs high-speed and high-precision analog-to-digital converter.Therefore, a new preamplifier chain design method is proposed, which can obtain very small LSB. The preamplifier input pipe size, to ensure a sufficiently small offset voltage under the premise of the input pipe at all levels to minimize the sum of the total.To verify the optimization method, combined with resistance equalization technology, the structure of a 3-level structure of the flash ADC. Compared with the general design, the total area of the input pipe is reduced by 57%. Each LSB is 3.125 mV and the direct conversion accuracy is 3.5 bit. Thanks to the window structure, the equivalent precision is 8 bit in the full input range and the sampling rate is 224 Msample / s.