Delay Optimized Architecture for On-Chip Communication

• 作 者: Sheraz Anjum Jie Chen Pei-Pei
• 机 构: InstitutcofInformationTechnology,InstituteofMicroelectronics
• 出 处: 中国电子科技：英文版
• 发表日期: 2009年2期
• 关键词: 网络架构 片上通信 时延优化 互连结构 网络模拟器 二维网格 系统单晶片 网络芯片 Index Terms-2D-Mesh networks-on-chip
• 基金项目: Manuscript received February 27, 2008, revised April 20, 2008. This work was supported by the National Natural Science Foundation of China under Grant No. 60425413 and COMSATS Institute of Information

Networks-on-chip(NoC),a new system on chip(SoC) paradigm,has become a great focus of research by many groups during the last few years.Among all the NoC architectures that have been proposed until now,2D-Mesh has proved to be the best architecture for imp