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针对在40Gb/s以太网规范中定义的循环冗余校验码(Cyclic Redundancy Code,CRC)计算关键路径过长的问题,提出了一种分块处理的方法来缩短每条关键路径的计算时间,从而满足时序的要求。对电路进行仿真,并使用中芯国际65nm工艺库进行综合。验证结果表明,提出的分块并行计算方法正确,并且能够提高CRC计算速度,满足时序要求。
Aiming at the problem of too much critical path calculated by cyclic redundancy check code (Cyclic Redundancy Code) defined in 40Gb / s Ethernet specification, a method of block processing is proposed to shorten the computation time of each critical path , To meet the timing requirements. The circuit simulation, and the use of SMIC 65nm technology library for synthesis. The verification results show that the proposed parallel block partitioning method is correct, and can improve the CRC calculation speed and meet the timing requirements.