A 8.75-11.2-GHz,low phase noise fractional-N synthesizer for 802.11a/b/g zero-IF transceiver

• 作 者: 梅年松 潘姚华 黄煜梅 洪志良
• 机 构: State Key Laboratory of ASIC & Systems,Fudan University,
• 出 处: 半导体学报
• 发表日期: 2011年06期
• 关键词: synthesizer transceiver fractional divide clock broadband modulator integer offs

An ultra broadband fractional-N frequency synthesizer for 802.11a/b/g zero-IF transceiver application is presented.The mathematical models for the behavior of the synthesizer’s spur and phase noise are analyzed,and the optimization methodology is proposed.Measurement results exhibits that the frequency synthesizer’s integrated phase noise is less than 1°(1 kHz to 100 MHz)with a 4.375 GHz carrier(after divide-by-2),and the reference frequency spur is below-60 dBc operating with a 33 MHz reference clock.The frequency synthesizer is fabricated on a standard 0.13μm RF CMOS process and consumes 39.6 mW from a 1.2 V supply voltage.

An ultra broadband fractional-N frequency synthesizer for 802.11a / b / g zero-IF transceiver application is presented. The mathematical models for the behavior of the synthesizer’s spur and phase noise are analyzed, and the optimization methodology is proposed. Measurement result exhibits that the frequency synthesizer’s integrated phase noise is less than 1 ° (1 kHz to 100 MHz) with a 4.375 GHz carrier (after divide-by-2), and the reference frequency spur is below-60 dBc operating with a 33 MHz reference clock. The frequency synthesizer is fabricated on a standard 0.13 μm RF CMOS process and consumes 39.6 mW from a 1.2 V supply voltage.