Design and Verification of High-Speed VLSI Physical Design

• 作 者: Dian Zhou Rui-Ming Li
• 机 构: Department of Electrical Engineering, The University of Texas at Dallas, Richardson, TX 75083-0688,
• 出 处: 计算机科学技术学报（英文版）
• 发表日期: 2005年2期
• 关键词: VLSI physical design floorplanning and placement interconnect delay wire sizing

With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement,interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis,parasitic extraction, and clock signal distribution are briefly reviewed.