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已经研究了一种新型的双极/CMOS工艺集电极注入技术2(CIT2),其光刻条宽为1.5μm。用标准双极工艺制造的LSI芯片,通常包括埋层、外延和隔离扩散等高温工艺,其成品率比MOS电路低,又难以与CMOS器件组合,因而就开发了注入集电极的新工艺。CIT技术既不采用外延,又不采用埋层,可以在双极或MOS生产线上实现。 用这种工艺制作了截止频率高(fT-5GHz)的npn晶体管,又作出了延迟时间为180ps的ECL门。非本征基极的整个表面为PtSi所覆盖,这样,它的电阻被降到20Ω。 n沟和P沟MOS晶体管的性能可与用常规的CMOS工艺制出的性能相媲美。在n阱内形成p沟MOS晶体管。p沟和n沟MOS晶体管的漏和源都直接与多晶硅相接,其最小传输延迟为280ps。
A new type of bipolar / CMOS process collector injection technology 2 (CIT2) has been studied with a lithographically wide strip width of 1.5 μm. LSI chips fabricated using standard bipolar processes, which typically include high-temperature processes such as buried layer, epitaxial, and isolated diffusion, yield less yield than MOS circuits and are difficult to combine with CMOS devices, resulting in the development of a new process for implanting a collector. CIT technology uses neither epitaxy nor buried layers and can be implemented in bipolar or MOS production lines. An npn transistor with a high cutoff frequency (fT-5GHz) was fabricated using this process, and an ECL gate with a 180ps delay was also made. The entire surface of the extrinsic base is covered by PtSi, so that its resistance is reduced to 20Ω. The performance of n-channel and p-channel MOS transistors is comparable to that of a conventional CMOS process. A p-channel MOS transistor is formed in the n-well. The p-channel and n-channel MOS transistors have their drain and source connected directly to polysilicon with a minimum propagation delay of 280 ps.