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在复分接系统中，如同步数字系列（SDH），定时处理占有重要地位。数字化定时处理技术应用于ASIC设计时，传统方法需要的仿真代价太大。作者指出了定时验证的特殊性，提出了定时处理电路验证的概念。同时利用参数化方法对定时处理进行验证，大大缩短了仿真时间。
In the complex system, such as synchronous digital hierarchy (SDH), timing processing occupy an important position. Digital timing processing technology used in ASIC design, the traditional method requires too much simulation cost. The author points out the particularity of timing verification and proposes the concept of timing processing circuit verification. At the same time using the parameterization method to verify the timing process, greatly reducing the simulation time.