论文部分内容阅读
When the voltage of an analog input signal is equal to the supply voltage,it is difficult for a conventional successive approximation ADC to correctly convert the analog signal into digital signal.This paper introduces an improved successive approximation ADC.which can convert the rail-to-rail input range and reduce sampling time through a track-and-hold circuit.Comparator offset cancellation and capacitor self-calibration techniques are used in this ADC.Measurement results show that the peak SNDR of this ADC reaches 72 dB and the signal effective bandwidth is up to 1.25 MHz.It consumes 1 mW in the test,and the figure of merit is 123 fJ/conversion-step.
When the voltage of an analog input signal is equal to the supply voltage, it is difficult for a conventional past approximationimation ADC. ADC to correctly convert the analog signal into a digital signal. This paper introduces an improved successive approximation ADC.which can convert the rail-to -rail input range and reduce sampling time through a track-and-hold circuit. Comparator offset cancellation and capacitor self-calibration techniques are used in this ADC. Measurement results show that the peak SNDR of this ADC reaches 72 dB and the signal effective bandwidth is up to 1.25 MHz. It consumes 1 mW in the test, and the figure of merit is 123 fJ / conversion-step.