ELIMINATING SPEED PENALTIES IN ECC PROTECTED MEMORY DESIGNS USING ＂BIT BYPASSING＂ TECHNIQUES

• 作 者: Zhi Tian Yang Haigang Cai Gang
• 机 构: InstituteofElectronics,UniversityofChineseAcademyofSciences
• 出 处: 电子科学学刊：英文版
• 发表日期: 2014年4期
• 基金项目: Supported by the National Science and Technology Major Project of China （No.2013ZX03006004）.

In deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories more vulnerable to reliability problems, such as soft errors induced by radiation. Error Correction Code(ECC) along with scrubbing is an efficient method f