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设计了一种用于CMOS图像传感器时钟产生的电荷泵锁相环(CPPLL)电路。基于0.18μm CMOS工艺,系统采用常规鉴频鉴相器、电流型电荷泵、二阶无源阻抗型低通滤波器、差分环形压控振荡器以及真单相时钟结构分频器与CMOS图像传感器片内集成。系统电路结构简洁实用、功耗低,满足CMOS图像传感器对锁相环低功耗、低噪声、输出频率高及稳定的要求。在输入参考频率为5MHz时,压控振荡器(VOC)输出频率范围为40~217MHz,系统锁定频率为160MHz,锁定时间为16.6μs,功耗为2.5mW,环路带宽为567kHz,相位裕度为57°,相位噪声为-105dBc/Hz@1MHz。
A charge pump phase locked loop (CPPLL) circuit is designed for CMOS image sensor clock generation. Based on the 0.18μm CMOS technology, the system uses conventional phase-frequency detector, current-mode charge pump, second-order passive impedance low-pass filter, differential ring voltage controlled oscillator and true single-phase clock structure divider and CMOS image sensor Integrated chip. System circuit structure is simple and practical, low power consumption, CMOS image sensor to meet the phase-locked loop low-power, low noise, high output frequency and stability requirements. When the input reference frequency is 5MHz, the VCO output frequency range is 40 ~ 217MHz, the system lock frequency is 160MHz, the lock time is 16.6μs, the power consumption is 2.5mW, the loop bandwidth is 567kHz, the phase margin 57 °, the phase noise is -105dBc / Hz @ 1MHz.